The Moore's Law put forward by one of the founders of Intel, Gordon Moore, has been guiding development of the semiconductor industry and the advancement speed of the information technology in the recent half century. As disclosed by Intel, the Moore's Law will still work in the coming 10 years. It is predicted that more than 1.024×1012 transistors will be integrated on a single chip in 2022.
However, the time has gone when the computing performance is enhanced by the clock speed alone, and performance enhancement of a central processing unit (CPU) is now bottlenecked by physical laws such as power consumption, interconnection delay, and design complexity. Due to the physical law bottlenecking, the change from single-core to multi-core (traditionally referring to less than 8 cores) or even many-core is inevitable, and is a result of interaction between the Moore's Law and the three physical laws. Many-core will be a main trend of future CPU architecture.
A multi-core/many-core processor scenario needs to allow for cache coherence, which may be solved by a software cache coherence mechanism or a hardware cache coherence mechanism. The software cache coherence mechanism primarily relates to two possible modes: a distributed shared memory (DSM) mode and a shared physical memory (SPM) mode. The DSM mode/SPM mode may be applied in a con-cache-coherent (NCC) many-core system to solve the cache coherence issue. In a single-chip cloud computer (SCC) developed by Intel, a Software Managed Cache Coherence (SMC) protocol adopts the SPM mode.